The present invention relates to computer processors in general and in particular to a high speed reduced instruction set computer implemented by a plurality of interconnected integrated circuits.
Advanced bipolar and gallium arsenide (GaAs) technologies permit the manufacture of high speed logic gates having propagation delays less than a nanosecond, and a computer processor utilizing such technologies would be exceptionally fast. However, it has generally not been feasible to implement very large scale integrated (VLSI) circuits using currently available advanced bipolar or GaAs technology because large numbers of bipolar logic gates dissipate too much power to be concentrated in a single integrated circuit, and because GaAs circuit fabrication processes have prohibitively low yields. Consequently, circuits implemented by such technologies have been limited to large or medium scale integration, rather than very large scale integration.
One way to increase the yield of an integrated circuit fabrication process, or to decrease the amount of power that an integrated circuit dissipates, is to decrease the complexity of the circuit being implemented in integrated circuit form. Simplified "reduced instruction set computer" ("RISC") processors have been proposed and constructed which reduce the amount of circuitry needed by reducing the number and complexity of instructions that the processors implement. Although RISC processors typically require more instructions to carry out certain operations than would more complex processors, it is believed that the decrease in processor performance due to the decrease in instruction set complexity can be more than offset by the increase in processing speed that can be obtained by utilizing higher speed integrated circuit technologies. However, reduced instruction set computers still require relatively large integrated circuits, and problems associated with low yield and high power dissipation have not been entirely solved by reducing the size and complexity of instruction sets.
Computer processors have been implemented utilizing hybrid circuits comprising several smaller scale integrated circuits mounted on a substrate and interconnected by microstrip conductors to overcome problems associated with low yields or high power dissipation of very large scale integrated circuits. However, partitioning of a high speed computer processor operating at high frequencies into a set of interconnected integrated circuits has not been feasible because signals transmitted between such integrated circuits would be of frequencies at which signal delay and reflections in microstrip conductors interconnecting the signals become problematic. In addition, operations of the various portions of a high speed computer processor are typically synchronized to a master clock signal, and variation in inherent delays of conductors conveying the master clock signal to each integrated circuit limits the frequencies at which the separate integrated circuits can exchange data with one another in a synchronous fashion, and therefore limit processing speed.